Article ID: 000077753 Content Type: Troubleshooting Last Reviewed: 02/10/2014

Why does Design Assistant not report a rule violation when my design uses a PLL locked signal as an asynchronous reset signal?

Environment

    Quartus® II Subscription Edition
    Reset
    PLL
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Description

Due to a problem in the Quartus® II software version 13.1 and earlier, Design Assistant does not report a rule violation when the locked signal of a PLL is connected directly to the asynchronous reset of a register.

When using the locked signal of a PLL as a reset, synchronize the signal to the destination clock domain to ensure correct timing analysis.

Resolution

This problem is scheduled to be fixed in the future release of the Quartus II software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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