Article ID: 000077726 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why does the Intel® Quartus® Prime Pro Edition Software fail to perform Simplex User Avalon Memory-Mapped Interface merging while using F-Tile IPs?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the Simplex Avalon Memory-Mapped Interface merging of Local User Avalon Memory-Mapped Interface does not work in F-Tile IPs.

    This affects the F-Tile PMA/FEC Direct PHY Intel FPGA IP and should also affect any other F-Tile IPs supporting simplex mode.

     

     

    Resolution

    Users who are trying to use two simplex IPs in the same hardware location should only enable Avalon Memory-Mapped Interface on one side, not the other. They can use that single enabled port to control Avalon Memory-Mapped Interface for both TX and RX.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series