Article ID: 000077725 Content Type: Error Messages Last Reviewed: 09/11/2012

Internal Error: Sub-system: SIM, File: sim_server.cpp, Line: 524


Description You may see this error in the Quartus® II software version 2.2 SP2 if incorrect bus member names are specified within a Vector Waveform File (.vwf). For instance, this error will occur if a bus member has a different naming convention, as follows.

One signal has the following entry: SIGNAL("|FPGA1|Logic_block:inst109|ac:inst1|data[23]"), and another signal has the following entry: SIGNAL("Logic_block:inst109|ac:inst1|data[24]")

The Quartus II software assumes that all children signals have the same name as the bus. Having a different name for a bus member will violate the rule that children signals have the same name as the bus.

To workaround this problem, modify the .vwf file or remove the register group and reinsert the node with the node finder.

This problem has been fixed in the Quartus II software version 3.0 to give an error message instead of an internal error.

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Stratix® FPGAs



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