Article ID: 000077683 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What IBIS model should I use to simulate the JTAG input pins TCK, TMS, TDI, and TRST in Stratix II devices?

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Description

You can use the 2s_ttl33_cin IBIS model to simulate the JTAG input pins TCK, TDI, TMS, and TRST in Stratix II devices. The JTAG input pins can be simulated using a 3.3V TTL input model for column pins since they are powered by VCCPD which is set to 3.3V in Stratix II devices.

Altera® provides IBIS models for the JTAG output pin TDO so you can model the output buffer behavior. Depending on the VCCIO of the bank where the pin resides, you can use either 2s_cmos15_tdo, 2s_ttl18_tdo, 2s_ttl25_tdo or 2s_ttl33_tdo IBIS models for simulation.

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Stratix® II FPGAs