The issue affects all Verilog configurations. VHDL designs are not affected.
If you require a Verilog instance of the RLDRAM II Controller, then two workarounds exist, as described below.
1. Continue to use your existing version 8.0 instance.
2. If you choose to update your existing instance, or if you do not have a version 8.0 instance, follow these steps to make the RLDRAM II Controller behave correctly. Edit the following files to change all instances of the line
else if (0)
to:
else if (1)
<variation name>_auk_rldramii_addr_cmd_reg.v
<variation name>_auk_rldramii_dqs_group.v
<variation name>_auk_rldramii_pipeline_addr_cmd.v
<variation name>_auk_rldramii_pipeline_qvld.v
<variation name>_auk_rldramii_pipeline_rdata.v
<variation name>_auk_rldramii_pipeline_wdata.v
Some files may only require editing if pipeline option is enabled in your RLDRAM II Controller variation.
This issue will be fixed in future version of RLDRAM II Controller.
