Article ID: 000077650 Content Type: Troubleshooting Last Reviewed: 04/12/2023

Why are the PCIe Hard IP SDC constraints for tl_cfg* ignored in my SOPC Builder design?

Environment

    PCI Express
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The PCI Express HardIP constraints for signals tl_cfg* are ignored in the SOPC Builder designs because the altpcierd_tl_cfg_sample module is not used in this mode.

As a result, in pcie_compiler_0.sdc, the SDC constraints that are placed after the comment below will be ignored:

# The following multicycle path constraints are only valid if the logic use to sample the tl_cfg_ctl and tl_cfg_sts signals

Note: These constraints are valid in the Platform Designer and Avalon® streaming HardIP configurations.

Resolution

N/A

Related Products

This article applies to 5 products

Arria® II GX FPGA
Arria® II GZ FPGA
Stratix® IV GX FPGA
Cyclone® IV GX FPGA
Stratix® IV GT FPGA

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