Article ID: 000077633 Content Type: Troubleshooting Last Reviewed: 03/04/2015

Why does my JESD204B design in Arria V generate a 0 PPM "Critical Warning (21196): Coreclk source from HSSI 8G..." during Quartus II fitter process?


  • Quartus® II Subscription Edition

    Due to a problem in the Quartus® II software version 13.1, when implementing a JESD204B design in the Arria® V family, Critical Warning (21196) is generated during the Quartus II fitter process, indicating that the PCS clocks do not have a 0 PPM relationship with respect to the link clock. An example of such a warning is shown below:

    Critical Warning (21196): Coreclk source from HSSI 8G RX PCS atom

    <pathname_to_core>:inst_av_hssi_8g_rx_pcs|wys does not have the same 0 PPM source with respect to internal  clock because of coreclk input of the receiver is not driven by rx clkout of its own channel


    Ensure that the JESD204B IP core txlink_clk and pll_ref_clk (transmitter variant) or tx_pll_ref_clk (duplex variant) has a 0 PPM clock relationship;  ensure that  the JESD204B IP core rxlink_clk and pll_ref_clk (receiver variant) or rx_pll_ref_clk (duplex variant) has a 0 PPM clock relationship. One such implementation is to derive link clock using core PLL as shown in Figure 4-8 of JESD204B IP core User Guide.

    After the JESD204B subsystem design is fully functional, to work around this Critical Warning, add the following .qsf assignment to each transceiver pin to eliminate these Critical Warnings:

    set_instance_assignment -name GXB_0PPM_CORECLK ON -to <transceiver pin name>

    Example: set_instance_assignment -name GXB_0PPM_CORECLK ON -to rx_serial_data[0]

    Related Products

    This article applies to 5 products

    Arria® V GX FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Arria® V GT FPGA
    Arria® V ST SoC FPGA



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