Article ID: 000077631 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are all the input clock frequency values shown in the ALTGX Megawizard Plug-in Manager for Stratix IV GX devices supported if a transceiver channel is configured at data rates above 6.5 Gbps?


  • Quartus® II Subscription Edition

    In the Quartus® II software versions 8.1 and earlier, for Stratix® IV GX devices only, the ALTGX MegaWizard® Plug-In shows multiple selectable input clock frequency values,  if the CMU PLL or RX CDR is configured for data rates above 6.5 Gbps.  However only one of values is valid.

    You must use the following equation to determine the supported input clock frequency value:

    Input clock frequency value = (CMU PLL or RX CDR data rate)/20

    Where "CMU PLL or RX CDR data rate" is defined as the value in the The base data rate is field on the General screen of the ALTGX MegaWizard® Plugin Manager.

    For example,  if  you configure a channel in a Stratix IV GX device to run at 8.5 Gbps data rate, the allowed input reference clock frequency value can be determined as follows:

    The base data rate is equals 8.5 Gbps.

    Therefore supported input reference clock frequency value = (8.5 Gbps/20) = 425MHz .

    So in this example, the ALTGX MegaWizard Plug-In shows the following input clock frequencies - 170 MHz, 212.5 MHz, 265.625 MHz, 340 MHz, 425 MHz and 531.25 MHz but only 425 MHz is a valid selection. 


    Related Products

    This article applies to 2 products

    Stratix® IV FPGAs
    Stratix® IV GX FPGA



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