Article ID: 000077624 Content Type: Error Messages Last Reviewed: 11/11/2011

Critical Warnings for Interlaken MegaCore Function 12- and 20-Lane Variations Without Transceivers

Environment

    Quartus® II Subscription Edition
    Interlaken
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Critical Issue

Description

When you compile an Interlaken MegaCore function 12- or 20-lane variation that excludes transceivers, the following warning message appears:

Critical Warning: (High) Rule C105: Clock signal should be a global signal. Found <num> node(s) related to this rule.

The warning message includes a list of rx_lane_clk<n>_export[<l>] signals, and if the out-of-band flow control block is included, some clock signals from that block.

Resolution

This issue has no workaround. However, this issue has no design impact. You can ignore this warning message.

This issue will be fixed in a future version of the Interlaken MegaCore function.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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