Article ID: 000077621 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How do I interface with the EPCS serial configuration device which requires 3.3V if the VCCIO of the bank in which my configuration pins resides is set to 1.8V for Stratix II and Stratix II GX devices?



For Stratix® II and Stratix II GX devices, when the VCCIO level of the bank in which your configuration pins reside is set to 1.8V and you wish to interface with an EPCS serial configuration device, you may consider using a voltage translator to raise the voltage on the FPGA dedicated configuration pin outputs that interface with the TTL 3.3V compatible inputs of the EPCS device. However it should be noted that as a voltage translator will introduce a finite delay to the configuration signals from the FPGA device, you could violate the timing of this interface whch could result in configuration failure.

Note that when VCCIO of bank 3 is 1.8-V and you wish to support configuration input voltages of 3.3-V, the VCCSEL pin must be connected to VCCPD.

Related Products

This article applies to 2 products

Stratix® II FPGAs
Stratix® II GX FPGA



All postings and use of the content on this site are subject to Terms of Use.