Article ID: 000077558 Content Type: Troubleshooting Last Reviewed: 08/23/2011

Power-Down Entry Command Timing Violation

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

ALTMEMPHY-based designs created with a version of the high-performance controller (HPC II) earlier than 11.0, with the Enable Auto Power Down option turned on, violate refresh to precharge command timing, breaching JEDEC requirement.

This issue affects all designs created in a pre-11.0 version of HPC II, with the Enable Auto Power Down option turned on.

Your design fails to simulate and doesn’t work in hardware.

Resolution

To meet the JEDEC requirement, perform the following steps:

  1. Open the alt_ddrx_bank_timer.v file.
  2. Locate the following command:
always @ (*) begin cs_can_power_down [w_cs] = power_saving_enter_ready [w_cs] & chip_idle; end

and change to:

always @ (posedge ctl_clk or negedge ctl_reset_n) begin if (!ctl_reset_n) cs_can_power_down [w_cs] <= 1\'b0; else cs_can_power_down [w_cs] <= power_saving_enter_ready [w_cs] & chip_idle; end

This issue will be fixed in a future version.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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