When designing an Intel® Arria® 10 FPGA DDR4 memory controller interface, you might see unconstrained DDR4 input and output ports. There should be false-path exceptions in the DDR4 SDC file for these signals.
The workaround for this problem is to add the following assignments to the DDR4 SDC file under the FALSE PATH CONSTRAINTS section:
set_false_path -to [get_ports {*dbi_n*}]
set_false_path -from [get_ports {*dbi_n*}]
set_false_path -from [get_ports {*alert_n*}]
set_false_path -to [get_ports {*mem_ck*}]
set_false_path -to [get_ports {*mem_ck_n*}]
set_false_path -to [get_ports {*mem_dqs_n*}]
This problem will be fixed in a future version of the Quartus® development software.