Article ID: 000077514 Content Type: Troubleshooting Last Reviewed: 04/24/2023

Why are the feedback clock and the output clock misaligned in External Feedback and Zero Delay Buffer (ZDB) modes?

Environment

    Quartus® II Subscription Edition
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Description

When external feedback mode or Zero Delay Buffer is selected as the compensation mode in Stratix® V, Arria® V, and Cyclone® V devices, the output clock will not have the expected phase relationship with the feedback clock. 

This is due to the Quartus® II software making incorrect delay chain settings in version 13.0 and earlier.

 

 

Resolution

If external feedback or ZDB modes are required, please submit a request to Altera technical support via mySupport.

Related Products

This article applies to 15 products

Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Stratix® V E FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA

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