Why do I see increased low frequency jitter when using the ATX PLL of Stratix V or Arria V GZ transceiver devices?

Due to a problem in the Quartus® II software you may see increased low frequency jitter when using the ATX PLL of Stratix® V or Arria® V GZ transceiver devices.

The Quartus II software sets the ATX PLL bandwidth to "Low" which can result in increased jitter in the 200kHz - 1.5MHz range. This can result in reduced margin for 3rd party receiver CDRs with low jitter bandwidth tracking capabilities.

To work around this problem you can set the ATX PLL bandwidth setting to "Medium" with a QSF assignment.

set_instance_assignment -name PLL_BANDWIDTH_PRESET MEDIUM -to <ATX PLL Instance>