Critical Issue
Description
This problem affects DDR3 products.
DDR3 interfaces on Stratix V devices may fail recovery analysis in the example design for transfers within the traffic generator. Such failures affect only quarter-rate designs and occur only inside the traffic generator. You can ignore these failures because they happen on transfers that do not require 1T timing.
Resolution
The workaround for this issue is to set the affected paths as false paths in the user-defined SDC files.
This issue will be fixed in a future version.