Article ID: 000077499 Content Type: Troubleshooting Last Reviewed: 02/02/2015

Why does the Native PHY IP core create the port "rx_pma_qpipullup" created when I enable "rx_qpi_pmapulldn"?

Environment

    Quartus® II Subscription Edition
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Description Due to a problem in the Quartus® II software version 13.1 Arria®10 edition and later, the "rx_pma_qpipulldn" port is erroneously named "rx_pma_qpi_pullup" on the module declaration.
Resolution

Even though the port is erroneously named, it functions as intended as "rx_pma_qpipulldn". Users should treat the "rx_pma_qpi_pullup" port as "rx_pma_qpipulldn".

This problem is fixed beginning with the Quartus II software version 14.1 Update 1.

Related Products

This article applies to 4 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 SX SoC FPGA
Intel® Arria® 10 GX FPGA

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