Why does my Nios II processor simulation fail when the data cache line size is set to 4 bytes?

You may encounter a simulation failure with the Nios® II processor when the data cache line size is set to 4 bytes.  The failures you may observe are:

• Failing to display character in simulation terminal when Nios II processor executes the character printing function
• Incorrect simulation results.

This issue is observed in Mentor Graphic Modelsim SE and Synopsys VCS simulation software when simulation optimization is turned on.

The simulation model for Nios II data cache memory shows different behavior when simulation optimization is turned on, which leads to the problem described.

This issue is observed in cases when Nios II processor is targeted to Stratix III/IV/V, Arria II/V and Cyclone III/IV/V device families.

To workaround this problem either:

• Turn off simulation optimization, by using – novopt flag in the simulation software.
• Set the Nios II processor data cache line size to either 16 or 32 bytes.