Article ID: 000077481 Content Type: Troubleshooting Last Reviewed: 09/11/2012

If I select the "Use shared PLL(s) for receiver and transmitter" option in the altlvds MegaFunction for the transmitter and receiver will the compiler use one or two PLLs?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description If you are using this option and the PLL settings are the same with the same input clock then the receiver and transmitter will use one PLL. If you have a different input clock or the PLL settings for the receiver and transmitter are different then two PLLs will be used.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs

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