No. The performance of the ODI circuit of an Intel® Stratix® 10 L/H-tile GXT channel operating at data rates above 17.4 Gbps can degrade over time if it is not enabled fulltime during the GXT channel operation. This problem does not affect the data path operational of the GXT channel. The performance of ODI circuit of a GX channel at data rates 17.4 Gbps and below is not affected.
If the ODI feature is required during the GXT channel operation, enable the ODI circuit fulltime to preserve its performance by setting the following register bits for each transceiver channel. It is not required to perform an eye scan to preserve the performance. After 3 years, its performance at GXT channel data rates may not be preserved even if it is enabled fulltime.
Change bits 2 and 0 of the GXT channel register address 0x168 from 1’b0 to 1’b1 via channel reconfiguration interface to enable ODI circuit.
To expose the reconfiguration interface ports, select the Enable dynamic reconfiguration option under the Dynamic Reconfiguration tab in the Native PHY IP.
To change the register through system console, select the Enable Native PHY Debug Master Endpoint option.
For details, refer to Reconfiguration Interface and Dynamic Reconfiguration chapter in the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.
For GX channels that are dynamic reconfigured to GXT mode, and if the ODI feature is required during GXT mode, enable the ODI circuit fulltime whether in GX or GXT mode.
Enabling the ODI circuit fulltime causes power increase of about 90 mW on VCCR_GXB and 70mW on VCCH_GXB per channel.