Article ID: 000077456 Content Type: Troubleshooting Last Reviewed: 06/15/2015

Timing analysis issue for Arria 10 devices in the Quartus II software version 15.0


  • Quartus® II Subscription Edition

    Critical Issue


    In the Quartus II software release version 15.0, the Fitter can incorrectly merge two registers with different timing exceptions (for example, false path or multicycle). The resulting register might have an incomplete list of assigned exceptions, resulting in incorrectly analyzed paths to and/or from the register. This issue can present as false timing violations or hardware failures. This issue only occurs with designs targeting Arria 10 devices.

    You might detect this issue if you generate a timing violation or if TimeQuest prints an exception ignored warning. Otherwise, detection of this problem is difficult.


    This issue will be fixed in an upcoming software release.

    If you detect this issue using the Quartus II software release verison 15.0, you can use the following workarounds:

    • Assign a PRESERVE_REGISTER pragma to the incorrectly duplicated registers
    • Disable TimeQuest2 by adding set_global_assignment -name TIMEQUEST2 OFF to your project\'s Quartus II Settings File (.qsf)
    • Disable register retiming, by selecting the Prevent register retiming check box under Assignments > Settings > Compiler Settings
    • Modify the Synopsys Design Constraints (SDC) to eliminate differences in the merged register\'s exceptions

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs



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