Article ID: 000077449 Content Type: Troubleshooting Last Reviewed: 11/11/2019

Why does the transmitter jitter increase when resetting adjacent transceiver channels?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
    Transceiver CMU PLL Intel® Arria® 10 Cyclone® 10 FPGA IP
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Description

You may observe increased jitter on an active transmitter channel with CMU PLL while resetting adjacent transceiver channels. This problem is caused when the CMU PLL high speed serial clock is enabled or disabled simultaneously on the adjacent channels, which causes a sudden local increase in the current consumption and jitter on the active transmitter channel.

Resolution

To work around this problem, use ATX PLL or fPLL instead of CMU PLL.

 

This problem will not be fixed in a future release of the Intel® Quartus® Prime Edition versions.

Related Products

This article applies to 6 products

Intel® Cyclone® 10 GX FPGA
Intel® Stratix® 10 GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 TX FPGA
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 SX SoC FPGA

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