Article ID: 000077445 Content Type: Troubleshooting Last Reviewed: 06/17/2023

Why aren’t the tx_polinv and rx_polinv ports available when using the transceiver Native PHY IP for Intel® Arria® 10 and Intel® Cyclone®10 devices in Enhanced PCS mode?

Environment

    Intel® Quartus® Prime Pro Edition
    Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The transceiver Native PHY Intel® Arria® 10 and Intel® Cyclone® 10 FPGA IP in Enhanced PCS mode does not have tx_polinv and rx_polinv ports. 

Resolution

You can use the Gearbox Enable RX data polarity inversion and Enable TX data polarity inversion settings to implement static polarity inversion. 

You can implement dynamic polarity inversion by reconfiguring the PHY with different Gearbox Enable RX data polarity inversion and Enable TX data polarity inversion settings.

Related Products

This article applies to 2 products

Intel® Cyclone® 10 FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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