Article ID: 000077438 Content Type: Troubleshooting Last Reviewed: 09/23/2019

Can I perform back to back writes to the Intel® Stratix® 10 and Intel Agilex® E-Tile Native PHY RS-FEC registers?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Stratix® 10 E-Tile Transceiver Native PHY
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, you can perform back to back writes to the Intel Stratix 10 and Intel Agilex E-Tile Native PHY RS-FEC registers.

    The E-Tile Transceiver PHY User Guide states the following in chapter “9.5. RS-FEC Registers”.

    “The delay between RS-FEC register reads should be at least10 μs.”

    There is no such requirement for register writes.

    Resolution

    This information will be added to a future version of the Intel E-Tile Transceiver PHY User Guide.

    Related Products

    This article applies to 3 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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