Article ID: 000077436 Content Type: Error Messages Last Reviewed: 04/29/2021

Error: (vlog-7) Failed to open design unit file "./../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_161/sim/altera_avalon_st_handshake_clock_crosser.v" in read mode.

Environment

    Intel® Quartus® Prime Pro Edition
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Description

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.4.

In Windows environment, you may find the following error message during simulation of Low Latency 10G MAC IP example design with Modelsim® when the maximum length of file path is beyond 260 characters

Error: (vlog-7) Failed to open design unit file "./../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_161/sim/altera_avalon_st_handshake_clock_crosser.v" in read mode.

 

Resolution

To avoid the error, reduce the directory depth of simulation files.

Related Products

This article applies to 3 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 GX FPGA

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