Article ID: 000077429 Content Type: Troubleshooting Last Reviewed: 06/16/2020

Why might my Stratix® IV GX device transceiver design fail to merge TX PLLs in the Quartus® II software?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Your Stratix IV GX device transceiver design fail to merge TX PLLs in the Quartus® II software if the TX PLLs within the ALTGX  Megawizard Plugin Manager to be merged do not have identical parameters.

    Resolution

    For the Quartus II software to merge TX PLLs, the settings, configuration, and inputs of those TX PLLs must be identical.

    Examples of TX PLL parameters that must be identical for successful merging are: clock inputs, control inputs like reset and powerdown, bandwidth settings, dynamic reconfiguration settings, PLL type.

    Related Products

    This article applies to 2 products

    Stratix® IV GX FPGA
    Stratix® IV GT FPGA