You can estimate transceiver E-Tile Channel PLL power for Intel® Stratix® 10 TX, MX, and DX devices in the Intel® Quartus® Prime PTC tool by adding a “Transmitter Only” line in the “Transceiver" page of the PTC.
The following three examples show how to configure the PTC for your desired E-Tile channel PLL requirements.
E-Tile Channel PLL configured for: Reference clock = 200MHz, pll_clkout1 = 800MHz, pll_clkout2 = 400MHz,
Operation Mode, Data Rate (Mbps), Digital/Analog Width, Power Mode, FEC, EHIP, Modulation, Digital Freq, #Refclks, Refclk Freq, VOD
Transmitter Only, 12800, 16 Normal Power, Bypass, Bypass, NRZ, 0, 1, 200, 0
E-Tile Channel PLL configured for: Reference clock = 125MHz, pll_clkout1 = 500MHz, pll_clkout2 = 250MHz,
Operation Mode, Data Rate (Mbps), Digital/Analog Width, Power Mode, FEC, EHIP, Modulation, Digital Freq, #Refclks, Refclk Freq, VOD
Transmitter Only, 8000, 16, Normal Power, Bypass, Bypass, NRZ, 0, 1, 125, 0
E-Tile Channel PLL configured for: Reference clock = 307.2MHz, pll_clkout1 = 491.52MHz, pll_clkout2 = 245.76MHz,
Operation Mode, Data Rate (Mbps), Digital/Analog Width, Power Mode, FEC, EHIP, Modulation, Digital Freq, #Refclks, Refclk Freq, VOD
Transmitter Only, 19660.8, 40, Normal Power, Bypass, Bypass, NRZ, 0, 1, 307.2, 0
Alternatively, you can instantiate an E-Tile Transceiver Native PHY IP in PLL mode in your Intel® Quartus® Prime project, compile the project, and view the configuration in the PTC.
This information will be added to a future revision of the Intel® FPGA Power and Thermal Calculator User Guide.