Due to a problem with the Arria® V Transceiver PLL Intel® FPGA IP core in Intel® Quartus® Prime Standard Edition version 18.1 software, you may observe error similar to above during Analysis & Elaboration compilation if the IP variation file type is VHDL.
Change the following in the <ip_instance_name> .vhd:
From
fboutclk(0) => fboutclk,
hclk(0) => hclk,
To
fboutclk(0) => fboutclk(0),
hclk(0) => hclk(0),
This problem is fixed starting with the Intel® Quartus® Prime Standard Edition software version 19.1.