Article ID: 000077407 Content Type: Troubleshooting Last Reviewed: 10/11/2019

Why does the bandwidth setting not change when using the fPLL Intel® Arria® 10/Cyclone® 10 FPGA IP in SDI_Direct mode?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • fPLL Intel® Arria® 10 Cyclone® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the fPLL Intel® Arria® 10/Cyclone® 10 FPGA IP in SDI_Direct mode, the bandwith setting is fixed to an optimal configuration. Hence changes to the bandwidth setting (Low, Medium, High) in this IP will not be applied to the generated MIF file. This is expected behavior.

    Related Products

    This article applies to 2 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs

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