Article ID: 000077396 Content Type: Troubleshooting Last Reviewed: 02/13/2019

Why does my Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP with 25Gbps lanes fail timing closure when targeting an Intel® Stratix® 10 E-tile Engineering Sample (ES) device?

Environment

    Intel® Quartus® Prime Pro Edition
    Interlaken (2nd Generation) Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Variants of the Interlaken (2nd Generation)  Intel® Stratix® 10 FPGA IP with 25Gbps lanes do not support Engineering Sample (ES) devices.

Resolution

In order to obtain the best “Quality of Result” for timing closure, launch Design Space Explorer II in the Intel® Quartus® Prime software and perform a seed sweep. 

Related Products

This article applies to 2 products

Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA

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