Article ID: 000077389 Content Type: Troubleshooting Last Reviewed: 09/02/2016

Why does my Arria 10 device fPLL report an unlocked condition when in fractional “precision k” mode?

Environment

• Intel® Quartus® Prime Pro Edition
• fPLL Intel® Arria® 10 Cyclone® 10 FPGA IP
• BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem with the Arria® 10 device fractional PLL (fPLL) hard lock detection circuit, the fPLL may report an unlocked condition when using fractional “precision k” mode.

When the fPLL is in fractional mode, the feedback counter value is a function of M and K(pll_dsm_fractional_division). The formula is “M (integer) K/2^32”.  Legal values of K are 1 through 2^32-1

The “K Factor” is defined as “pll_dsm_fractional_division/2^32”,

When the K Factor is less than 0.1 or greater than 0.9, the fPLL hard lock detection circuit is unreliable.

When the K Factor is between 0.1 and 0.9, the fPLL hard lock detection circuit is reliable.

Example

The example below describes when the Arria 10 fPLL lock detection circuit is and isn’t reliable.

refclk (frequency) = 100MHz

N counter = 1

M counter = 40

K counter (pll_dsm_fractional_division) = 2147483648

L counter = 4

PLL output (frequency) = ( refclk (frequency) / N)  * ( ( M ( K / 2^32) ) / L )

In this case,

PLL output (frequency)        = 100 * ( ( 40 ( 2147483648 / 2^32) ) / 4 )

= 100 * ( ( 40   0.5 ) / 4)

= 100 * ( 40.5 / 4 )

= 100 * 10.125

= 1012.5 MHz

Because the fractional value is 0.5 (2147483648 / 2^32, with K = 2147483648) and it is between 0.1 and 0.9, the lock signal is reliable.

Resolution

When the fractional value is less than 0.1 or greater than 0.9, the fPLL lock signal is unreliable. In this case you can instantiate the following soft IP lock detection logic

The soft_lckppm_det.v file is encrypted but can be used for synthesis, simulation, and hardware testing.

The port list and description of the soft lock detection circuit file is below

 Port Name Input/Output Description ref_clk Input Reference clock input for fpll clk_low Input Clock low from fpll, always toggles, frequency might be off output reg pll_locked dead_ref_clk Output Indicates the reference clk doesn’t toggle fast enough and is considered as dead. The default threshold is defined by the module parameter PPM_THRESHOLD_FOR_DEAD_CLK calibration_done Input cal_done from fpll. Can be considered as secondary reset config_en Input Configuration port enable config_clk Input Configuration port clock config_data Input Configuration port data. When config_en is high, the data is sampled at the rising edge of config_clk and shifted into the internal registers storing thresholds for lock and dead clock conditions. The register width is defined by module parameter CLK_LOW_CNT_WIDTH. Therefore, the total cycles needs to shift in all data is 2* CLK_LOW_CNT_WIDTH cycles.  The shifting operation starts at the LSB of register for lock condition. After 2* CLK_LOW_CNT_WIDTH cycles, the value on config_data will become the MSB of register for dead_lock condition reset Input reset from fpll