Article ID: 000077378 Content Type: Troubleshooting Last Reviewed: 07/25/2017

What is XCVR_TX_PRE_EMP_2ND_POST_TAP_USER range for Arria V, Stratix V SG / GX?

Environment

    Intel® Quartus® Prime Pro Edition
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Valid XCVR_TX_PRE_EMP_2ND_POST_TAP_USER range is positive values between 0 and 31 and value mapping rules with XCVR_TX_PRE_EMP_2ND_POST_TAP are shown in the following table.

XCVR_TX_PRE_EMP_2ND_POST_TAP_USER values includes sign info while XCVR_TX_PRE_EMP_2ND_POST_TAP requires a sign bit. XCVR_TX_PRE_EMP_2ND_TAP_USER uses 1-15 for negative values and 17-31 for positive values without sign bit while XCVR_TX_PRE_EMP_2ND_POST_TAP assigns common values, 0-15 with sign bit.

XCVR_TX_PRE_EMP_2ND_POST_TAP_USER

XCVR_TX_PRE_EMP_2ND_POST_TAP

1 to 15

-15 to -1

17 to 31

1 to 15

0 and 16

0

Related Products

This article applies to 4 products

Stratix® V GX FPGA
Intel® Programmable Devices
Arria® V GZ FPGA
Stratix® V GS FPGA

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