Description
Due to description problem of UG-01143 | 2019.12.13, you will see the minimum duration of pll_powerdown of Intel® Arria® 10 TXPLL is 70us in document, this is incorrect. This duration didn't match the Transceiver PHY Reset Controller Intel FPGA IP Arria/Cyclone 10 Default Settings which is 1us.
Resolution
This problem has been fixed in UG-01143 | 2020.05.15.