Article ID: 000077371 Content Type: Troubleshooting Last Reviewed: 09/11/2020

What is the pll_powerdown minimum duration requirement of Intel® Arria® 10 TXPLL?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to description problem of UG-01143 | 2019.12.13, you will see the minimum duration of pll_powerdown of Intel® Arria® 10 TXPLL is 70us in document, this is incorrect. This duration didn't match the Transceiver PHY Reset Controller Intel FPGA IP Arria/Cyclone 10 Default Settings which is 1us. 

    Resolution

    This problem has been fixed in UG-01143 | 2020.05.15.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 GX FPGA