Article ID: 000077360 Content Type: Troubleshooting Last Reviewed: 11/15/2024

Can the start_of_burst and end_of_burst signals be asserted at the same time for the Serial Lite III FPGA IP on Arria® 10 and Stratix® 10 devices?

Environment

    Intel® Quartus® Prime Pro Edition
    Serial Lite III Streaming Intel® FPGA IP
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Description

Yes. The Serial Lite III FPGA IP supports a minimum one cycle burst length for the source data interface. You can assert the start_of_burst and end_of_burst signals on the same clock cycle for one cycle source data.

Resolution

N/A

Additional information

N/A

Related Products

This article applies to 2 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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