Article ID: 000077358 Content Type: Troubleshooting Last Reviewed: 02/03/2017

Why do I see Arria 10 device transceiver errors when using the Native PHY IP Configuration Profiles feature?


  • Intel® Quartus® Prime Pro Edition
  • Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP

    Due to a bug in the Arria 10 device Native PHY IP, designs that use the Configuration Profiles feature may contain paths which are not timing analysed if the Native PHY IP is generated anywhere other than the Quartus Prime Project folder.

    Transceiver timing information for each of the Configuration Profiles is contained in the IP generated <filename>.json files which are referenced by the Native PHY IP <filename>.qip file.

    The configuration profiles generated by the Native PHY IP are location sensitive. If the Native PHY IP is generated anywhere other than the Quartus Prime project folder, the <filename>.json files are missed. The project will successfully compile without analysing the <filename>.json timing files however the timing arcs for the non-default configuration profiles will be missing.

    No warning is provided by the Quartus Prime software.

    In this scenario, the default Native PHY IP configuration is timing analysed, but the alternate configuration profiles are not.

    How can I tell if my design is affected?

    You can check your Quartus Prime project to see if you are affected with the attached check_transceiver_profiles.tcl script. The script identifies missing <filename>.json files and potential missing timing arcs. You can source the file from the Quartus Prime Tools > TCL Scripts dropdown menu. The output of the script can be seen in the System tab of the Messages window.

    Workaround 1

    Ensure that the Native PHY IP is placed in the Quartus Prime project folder. You can do this by placing the <filename>.qsys file in the same folder as the <project_name>.qpf file. You can then regenerate the IP from this location.

    Workaround 2

    Modify the relative paths to “all” .json files within the following IP generated file:

    \<qsys file location>\<ip variant name>\altera_xcvr_native_a10_16*\synth\<ip variant name>_altera_xcvr_native_a10_16*_*.sv



    // reconfig_settings

            .hssi_10g_rx_pcs_reconfig_settings("./<IP variation name>/altera_xcvr_native_a10_16*/synth/rcfg_timing_db/hssi_10g_rx_pcs_reconfig_settings_*.json"),

            .hssi_10g_tx_pcs_reconfig_settings("./<IP variation name>/altera_xcvr_native_a10_16*/synth/rcfg_timing_db/hssi_10g_tx_pcs_reconfig_settings_*.json"),



    // reconfig_settings

            .hssi_10g_rx_pcs_reconfig_settings(“<IP(.qsys) location relative to project>/<IP variation name>/altera_xcvr_native_a10_16*/synth/rcfg_timing_db/hssi_10g_rx_pcs_reconfig_settings_*.json"),

            .hssi_10g_tx_pcs_reconfig_settings(“<IP(.qsys) location relative to project>/<IP variation name>/altera_xcvr_native_a10_16*/synth/rcfg_timing_db/hssi_10g_tx_pcs_reconfig_settings_*.json"),


    How can I analyze my pre-placed and routed design using these workarounds?

    After applying either of the workarounds mentioned above you can rerun the TimeQuest Timing Analyzer from the Quartus Prime Processing>Start>Start TimeQuest Timing Analyzer drop down menu.

    For users performing timing analysis directly in the TimeQuest GUI then you must use the “create_timing_netlist -force_dat” command after applying either workaround to create the timing netlist with the updated timing information.


    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs