Article ID: 000077355 Content Type: Install & Setup Last Reviewed: 07/13/2017

Why can't I generate the Arria 10 device SerialLite III design example in Quartus Prime Standard editions 16.0, 16.1 and 17.0?

Environment

    Intel® Quartus® Prime Standard Edition
    Serial Lite III Streaming Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Standard edition software versions 16.0, 16.1 , and 17.0, you may not be able to generate the Arria® 10 device SerialLite® III design example.

The design example generation may hang with the following information in the dialog box:

seriallite_iii_a10_0: Generating testbench components for simulation

Info: seriallite_iii_a10_0: Generating simulation kick-off scripts

Info: seriallite_iii_a10_0: Generating tcl files for QSYS generation

Resolution

To fix this problem install the Quartus Prime Stratix® V device package.

This problem will be fixed in a future version of the Quartus Prime software.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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