Why are the Intel® Stratix® 10 Ethernet 100G Design Examples unable to interop with Ethernet switch and send packets to the switch?

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1 and later, you may observe the Ethernet switch dropping all the packets sent from the Intel® Stratix® 10 device when using the following Intel Ethernet IP Design Examples:

• E-tile Hard IP Intel® Stratix® 10 Design Examples
• H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example
• Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example

The Ethernet switch does not support the specified type/length field of Ethernet frame in the above Design Examples.

To fix the problem, modify the alt_aeuex_packet_client_tx.v file in <design_example_dir>/hardware_test_design/common/ directory to change the payload length to 0x88b5 and recompile the design.

Replace the following statement:

dout_next  = {DEST_ADDR, SRC_ADDR, {2'b00,payload_length},index, {6{rjunk}}};

with:

//dout_next  = {DEST_ADDR, SRC_ADDR, {2'b00,payload_length},index, {6{rjunk}}};

dout_next  = {DEST_ADDR, SRC_ADDR, {16'h88b5},index, {6{rjunk}}};