Article ID: 000077348 Content Type: Troubleshooting Last Reviewed: 11/18/2020

Why does the transceiver E-Tile Native PHY IP Embedded Streamer hang when performing transceiver dynamic reconfiguration on Intel Stratix 10 TX, DX, and MX devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in the Windows version of the Intel® Quartus® Prime software version 19.4 and earlier, the transceiver E-Tile Native PHY IP Embedded Streamer may hang when performing transceiver dynamic reconfiguration on Intel Stratix® 10 TX, DX, and MX devices. The Linux version of the Intel Quartus Prime software is unaffected.

    The Intel Stratix 10 E-Tile Native PHY IPs generated using the Windows version of the Intel Quartus Prime software version 19.4 and earlier may have an incorrect last word of the transceiver configuration file.

    Resolution

    To work around this problem you can generate your Intel Stratix 10 device E-Tile Native PHY IP using the Linux version of the Intel Quartus Prime software.

    Alternatively you can edit the final word of the transceiver configuration file in the following location.

    ..\<phy_name>\altera_xcvr_native_s10_htile_<quartus_version>\synth\ alt_xcvr_native_rcfg_strm_params_<random_string>.sv file

    For example:

    ..\LH_PHYDxUSR0_x1\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_rcfg_strm_params_df5ou5a.sv

     

    Edit the file so that the most significant non-zero nibble is “7” hex.

    For example:

    Change the final word from 27'h000FFFFFF to 27'h007FFFFFF

    Or change the final word from 35'h0FFFFFFFF to 35'h7FFFFFFFF

     

    This problem is fixed in the Intel Quartus Prime software version 20.2.

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 DX FPGA