Article ID: 000077347 Content Type: Error Messages Last Reviewed: 08/18/2021

Error(21636): QSF assignment PRESERVE_UNUSED_XCVR_CHANNEL has been specified to preserve unused transceiver channels in HSSI IO BANK 9A.

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Error(21636): QSF assignment PRESERVE_UNUSED_XCVR_CHANNEL has been specified to preserve unused transceiver channels in HSSI IO BANK 9A. However, no reference clock has been specified using the QSF assignments set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_BTI_clock=TRUE" and set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=". See E-tile User Guide for more information.

     

    User will meet this error when upgrade design to the Intel® Quartus® Prime Pro Edition software version 20.1 with a global assignment PRESERVE_UNUSED_XCVR_CHANNEL for unused transceiver channels in completely unused tiles.

    Resolution

    To preserve all unused channels in completely unused tiles, user need follow the steps below:

    1. Add refclk port in top-level design for each tile.
      For example:
          module top (
              input wire refclk_preserve_0,
                  ......
              );
    2. Add assignments on refclk pin (valid frequency range is 125MHz-500MHz)
      For example:
          set_location_assignment PIN_AT13 -to refclk_preserve_0
          set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_BTI_clock=TRUE" -to refclk_preserve_0
          set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=156250000" -to refclk_preserve_0
    3. Add global assignment to preserve unused channels
      For example:
          set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON 

    Related Products

    This article applies to 4 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 DX FPGA

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