Article ID: 000077294 Content Type: Troubleshooting Last Reviewed: 09/02/2012

What is the DLL jitter specification for external memory interfaces and does the DLL jitter change depending on the frequency of operation?



The DLL & DQS logic blocks are designed to reject input jitter. The DLL uses gray-coded values for the control word to avoid jitter when DQS delay settings change. And use dual-phase detector blocks to ensure any change in control word is only made when the up or down signal is stable for four consecutive cycles.


The only uncertainty on the DQS clock path is introduced by resolution of the delay steps. This uncertainty is a function of the number of DQS delay stages used, and not dependent on the clock frequency or memory interface standard. This uncertainty is specified as DQS phase shift error and included in the ALTMEMPHY & UniPHY timing analysis scripts.


You can get the DQS phase shift error specification from the device datasheet, for example DC and Switching Characteristics (PDF) chapter of the Stratix IV handbook, table 1-46 gives the specification for DQS phase shift error.


Related Products

This article applies to 4 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA
Stratix® III FPGAs



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