Do Altera simulation models accurately model PLL clock switchover?

The simulation models do not properly represent actual Altera® device behavior for all combinations of clock input operation for PLL manual clock switchover. The simulation models may show a successful clock switchover when the clkswitch signal is asserted during a period of no transitions on one or both of the input clocks.

When using manual clock switchover, both input clocks must be available at the inclk[1..0] ports of the PLL for the switchover event to be successful. This is a requirement as shown in the respective device handbook.