Article ID: 000077280 Content Type: Product Information & Documentation Last Reviewed: 08/13/2012

How does the of the PCI Express Hard ECC buffer function work?



The PCI Express Hard IP Receive buffer and Transmit Retry buffer implement ECC MRAM protection as an option in the MegaWizard.

Each ECC encoder and decoder block has three signals which are:

  • derr_cor_ext_rcv[1:0]: This indicates a correctable error in the Rx buffer for the corresponding virtual channel (rvc).
  • derr_cor_ext_rpl: Indicates a correctable error in the retry buffer.
  • derr_rpl: Indicates an uncorrectable error in the retry buffer.

These signals are synchronized to the core_clk, have a duration of one clock cycle, and are active only during the memory read cycle from the corrupted location.

The derr_cor_ext_rcv[1:0] and derr_cor_ext_rpl signals indicate that an ECC correctable error has been detected, and corrected automatically by the ECC function.

When a correctable ECC error occurs, the PCI Express Hard IP will automatically recover the data without any loss of information.

When an uncorrectable ECC error occurs, the corrupt data in the retry buffer is erased. The user application layer must handle this case according to the application requirements. It is not necessary to reset the PCI Express Hard IP, but the user application layer may require this.

Related Products

This article applies to 2 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA



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