DDR3 Interfaces with Multiple mem_ck signals May Produce No-Fit Errors

This problem affects DDR3 products.

DDR3 memory interfaces with mem_ck width greater than one, targeting Arria V or Cyclone V devices, may encounter a no-fit error similar to the following:

Error (175020): Illegal constraint of DQS Group to the region (2, 0) to (22, 0): no valid locations in region Info (175028): The DQS Group name: DQS_LOGIC_BLOCK_5~DQ_X8/9 Info (175015): The I/O pad is constrained to the location PIN_AP28 due to: User Location Constraints (PIN_AP28) Error (171000): Can't fit design in device

The workaround for this issue is as follows:

1. Open the file xxx_addr_cmd_pads.v in a text editor.
2. Search for the localparam USE_ADDR_CMD_CPS_FOR_MEM_CK and set its value to true.

This issue will be fixed in a future version.