Article ID: 000077183 Content Type: Troubleshooting Last Reviewed: 04/12/2023

Why does the Stratix® V Hard IP for PCI Express fail to complete DMA transactions when using the Descriptor Controller interface?

Environment

    Quartus® II Subscription Edition
    DMA
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Description

Due to a problem with the Descriptor Controller IP, simultaneous DMA read-and-write operations with the Stratix® V Hard IP for PCI Express for Avalon® Memory-Mapped Interface with DMA core might stop DMA transaction before completion.

Resolution

To work around the problem, after a whole DMA read completes, start a DMA write (or, after a whole DMA write completes, start a DMA read).

This problem is fixed in Quartus® software version 14.0.

Related Products

This article applies to 3 products

Stratix® V GX FPGA
Stratix® V FPGAs
Stratix® V GT FPGA

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