The User Guides for PCI Express Do Not Document How a Variant Handles the Address Translation and Reserved Bits of a TLP Header

The PCI Express Base Specification states that receivers can optionally check the Address Translation (AT) bits of the Transaction Layer Packet (TLP) and flag the received TLP as malformed if AT is not 2’b00. The Arria V, Cyclone V, and Stratix IV devices do not perform this check. When these devices forward the TLP to the Application Layer, they set these bits to the value of zero.

In addition, when these devices forward the TLP to the Application Layer, they zero reserved bits [3:0] of Byte 1 of the TLP header. Root Ports set the reserved bit [7] of Byte 0 of the TLP header to 1 if the TLP is forwarded in response to the assertion of the app_msi_req input pin; otherwise, Root Ports set this reserved bit to 0. Reserved bit [7] is always 0 for Endpoints.

No workaround is required; however, you cannot rely on the AT bits to flag malformed TLPs. This issue is documented in version 12.0 of the Arria V Hard IP for PCI Express User Guide and Cyclone V Hard IP for PCI Express User Guide.