The race condition between control signals (HighZ and mdorhz) within the JTAG boundary scan cell (BSC) to IO buffer trigger the default value in BSC shifted out to output buffer prior to usermode.
The default value in BSC upon power-up is un-deterministic which may enable the OE register which may cause the sag to occur.
This behavior will neither cause any functional failure nor reliability concern on the device.
Option 1: Shift all “1” in to boundary scan cell
- Execute SAMPLE instruction
- Shift Data register with all “1” to disable all OE registers
- Execute BYPASS instruction
- Program the device
Option 2: Enable ISP clamp feature
- Enable ISP clamp feature to clamp the IO pin to tristate or high/low
o The default setting in the .ips file for all pins are tristate
o Add the .ips file in the programmer and enable the ISP clamp
o Ensure that the clamp value matches the polarity of the connected external resistor if the IO pin is clamped to high or low
o Internal weak pull-up resistor will be disabled when ISP clamp is used