Article ID: 000077155 Content Type: Troubleshooting Last Reviewed: 01/20/2015

Why does an M20K memory incorrectly show error status on the eccstatus port when the initial content data is read out?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 14.0 and earlier, an M20K memory may incorrectly show error status on the eccstatus port when the M20K is used as 2-port RAM with following 2 options and the initial content data is read out in Stratix® V.

    • Enable error checking and correcting (ECC) to check and correct single bit errors, double adjacent bit errors and detect triple adjacent bit errors in the Clks/Rd,Byte En tab
    • Yes, use this file for the memory content data in the Mem Init tab

    The error is shown only when the initial content data is read.  After the initial content data is overridden with new data by write operation, the eccstatus port outputs correct status for the new data.

    Resolution

    To work around this problem, use 512 words of memory depth regardless of your target memory depth.  Note that if you target memory depth is smaller than 512 words, you need to connect the extra MSB inputs of write and read address to dummy logic to avoid them being synthesized away. 

    To fix this problem, download and install Patch 4.50 for the Quartus II software version 13.1.4 from the appropriate link below.

    This problem is fixed beginning with the Quartus II software version 14.1.

     

    Related Products

    This article applies to 4 products

    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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