Article ID: 000077138 Content Type: Troubleshooting Last Reviewed: 07/09/2014

Why is the reference clock frequency set incorrectly when I update the Hard IP for PCI Express?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a bug when you change the reference clock frequency for an existing IP Compiler for PCI Express® (PCIe), the new reference clock frequency is not updated in the transceiver used by the PCIe IP core.
    Resolution

    To work around this issue, follow these steps to change the reference clock for an existing PCIe IP variant.

    1. Delete the serdes variant (<variant>_serdes.v).
    2. Update the reference clock in the MegaWizard Plug-in Manager.
    3. Regenerate the PCIe variant.

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    This article applies to 9 products

    Cyclone® IV FPGAs
    Cyclone® IV GX FPGA
    Arria® GX FPGA
    Arria® II GX FPGA
    Arria® II GZ FPGA
    Stratix® GX FPGA
    Stratix® II GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV GX FPGA

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