Article ID: 000077133 Content Type: Troubleshooting Last Reviewed: 07/06/2016

Why are the Frame Buffer II IP core dout_data, master_wr_writedata and master_rd_readata signals shown as unknown during simulation?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Quartus® Prime software version 15.1, you may observe the Frame Buffer II IP core dout_data, master_wr_writedata and master_rd_readata signals showing as unknown during simulation. Hardware operation is not affected.

Resolution This problem is fixed beginning with the Quartus Prime software version 16.0.

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This article applies to 1 products

Intel® Programmable Devices

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