Description
Due to a problem in the Quartus® II software version 12.0 and later, you may see this error message when compiling your gate-level VHDL netlist in the ModelSim simulator. This error occurs if your design constains an ALTDDIO_OUT instance.
Resolution
To work around this problem, turn off the Maintain hierarchy option for the EDA Netlist Writer by following the steps below:
- Select Settings from Quartus II Assignments menu
- In the Settings dialog box, click on Simulation under EDA Tool Settings in the Category pane
- Click on More EDA Netlist Writer Settings
- Turn off the Maintain hierarchy option
This problem is scheduled to be fixed in a future release of the Quartus II software.