Article ID: 000077086 Content Type: Product Information & Documentation Last Reviewed: 06/05/2013

How can I enable the use of the Txs slave port of PCIe Avalon-MM interface?

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Description To enable the use of the Txs slave port, the Master Enable bit (bit 2) in the PCIe® configuration space register at offset 0x4 has to be set to '1' via the CRA interface. (It is also observed at bit 2 of cfg_prmcsr). Without setting Master Enable bit to '1', TxsWaitRequest_o signal stays at '1' and it does not accept read and write transactions. 

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